The present invention relates to reference voltage generators and, more particularly, to reference voltage generators which must provide a reference voltage quite near the value of voltage provided by a power supply in a plurality of power supplies.
Electronic circuit systems often require provision therein of precise values of voltage for many different purposes. Among these purposes is the provision of a reference level about which switching between logic states occurs in certain kinds of logic gate circuits. One class of logic circuits in which this is used is the well known class of current mode logic (CML) gate circuits.
CML logic gates are typically formed about a pair of npn bipolar transistors having the emitters thereof connected together and to a current sink. Each collector of this pair of transistors is connected through a corresponding collector load resistor to the CML logic gate supply voltage provided with respect to the ground reference voltage or datum voltage. The base of one of the transistors serves as an input of the logic gate and, if further gate inputs are required, additional bipolar transistors can be provided, each having its base as a gate input and each having its emitter connected to the emitter of, and its collector connected to the collector of, that transistor already serving as a gate input.
The other transistor in the original pair of emitter-connected bipolar transistors forming a CML logic gate, or the reference transistor, has its base connected to a reference voltage which sets the voltage value about which input voltages can switch the gate from one logic state to another, i.e. the input voltage switching range. Thus, a voltage on the base of the logic gate input transistor of the emitter-connected pair of a sufficient magnitude will switch that transistor sufficiently "on" to supply the current demanded by the current sink and raise the voltage at the emitter thereof sufficiently to result in switching the other transistor in the pair, or the reference transistor connected to the reference supply, into the "off" condition. Similarly, a sufficiently low voltage applied to the base of the input transistor will lead to the input transistor being switched into the "off" condition, and with the current for the current sink supplied by the reference transistor. Thus, two different voltage levels can be established across each of the collector load resistors of this emitter-connected pair of transistors to result in two different logic states across each being represented thereby. The state at any one time across one resistor is, of course, the complement of that across the other.
These voltages across the collector loads of the emitter-connected transistors have a close relationship with the voltage value of the supply connected thereto. Since the current sink demands a substantially constant current, and either one or the other of these transistors is in the "off" condition, the voltage occurring across either load resistor for its corresponding transistor being "on" in one logic state will be substantially constant since a fixed current flows therethrough. The voltage at the transistor collector then will have a fixed relationship to the voltage value of the power supply to which the other end of its resistor is connected. Of course, for either of these transistors being in the "off" condition, the voltage occurring at its collector will be the power supply voltage. Thus, if the gate circuit outputs are taken at the collectors of the emitter-connected pair of transistors where each is connected to one of these resistors, the outputs will vary with variations in the gate supply voltage value, with respect to ground, but will remain essentially constant with respect to this power supply voltage value.
Since the logic gate output voltages representing logic states will usually be used to operate one or more succeeding logic gates of this same type, the variation in output voltage with changes in the value of the power supply connected to the load resistors in a CML logic gate can lead to difficulty. Such succeeding logic states, if the input voltage range in such gates for switching between logic states remains fixed, may have the gate output voltage values of a preceding gate connected to its input drift to values outside part of this input voltage switching range. Thus, there is a substantial value in having the reference voltage for the reference transistor in the emitter-connected pair vary with the supply voltage to the CML logic gates so that the gate input switching ranges for switching between logic states will, in effect, vary in the same way that the output voltage ranges between the logic states vary with respect to the gate supply voltage.
Thus, there is a desire to provide a reference voltage at the base of the reference transistor in the emitter-connected transistor pair forming a CML logic gate that varies in correspondence with changes in the CML logic gate voltage supply. A typical voltage for a CML logic gate supply is 3.3 V.+-.5%. The voltage value for the voltage reference for such a CML logic gate operated at such a supply voltage might typically be 3.1 V at room temperature. Thus, there will be substantial difficulty in providing such a voltage reference using the CML logic gate supply voltage because of the small voltage difference between them. This small difference would lead to requiring a pass transistor to operate with a few tenths of volts thereacross, or less, which presents substantial circuit difficulties.
Fortunately, many monolithic integrated circuits using CML logic gates therein also use transistor-transistor logic (TTL) gates to provide sufficient signal strength for operating certain kinds of circuits such as those on different integrated circuit chips. The typical voltage supply value for TTL logic circuits is 5.0 V.+-.10%. Thus, a source of a larger value voltage is typically available for use by a reference generator in providing the reference voltage necessary for operating CML logic gates. However, the wide voltage value ranges in which these two voltage supplies operate, given the tolerances indicated for them above, can lead to substantial difficulties in providing the desired reference voltage. Thus, there is desired a reference voltage generator which can provide a reference voltage for CML logic gates that follows changes in the CML logic gate supply but can tolerate the changes occurring in the TTL gate and the CML gate voltage supplies.